UVM in Systemverilog- 3: Learn The Architecture & Code Your VIP
9 modules · 34 videos
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SystemVerilog AcademyYour VLSI Companion
Courses
UVM
UVM in Systemverilog -2: Writing Reusable Agents in UVM
Intermediate level course teaching t how to write a profession code for a UVM Agent
- Modules
- 6
- Lessons
- 16
- Ready
- 15
- Duration
- 2h 04m
Lesson path
Modules and lessons
Each module keeps the academy sequence intact and opens available lessons directly on YouTube.
01Welcome1/1 lessons · 2m
- 1.1WelcomeCourse : UVM in Systemverilog 2 : L1.1 : Welcome2:22Watch
02Generic UVM Testbench Structure1/1 lessons · 3m
- 2.1Generic UVM Testbench StructureCourse : UVM in Systemverilog 2 : L2.1 : Generic UVM TB Structure3:09Watch
03Concept of Reusable Agents2/3 lessons · 16m
- 3.1Concept of Reusable agentsCourse : UVM in Systemverilog 2 : L3.1 : Concept of Reusable UVM Agents & General Structure10:00Watch
- 3.2Reusable Agents StructureCourse : UVM in Systemverilog 2 : L3.2 : Block Diagram of Complet AXI Agent with 5 Channel6:04Watch
- 3.3Complete AXI Agent with 5 Channel Block DiagramPending
04Writing Dummy Design3/3 lessons · 26m
- 4.1Writing Dummy Design ComponentsCourse : UVM in Systemverilog 2 : L4.1 : Writing Dummy Design Components9:54Watch
- 4.2Writing Testbench & ConfigsCourse : UVM in Systemverilog 2 : L4.2 : Writing Testbench and UVM Config DB Settings11:01Watch
- 4.3Writing AXI TransactionCourse : UVM in Systemverilog 2 : L4.3 : Writing AXI Transaction Class5:15Watch
05Writing AXI Agent7/7 lessons · 1h 14m
- 5.1AXI Write Address Master DriverCourse : UVM in Systemverilog 2 : L5.1 : Writing AXI Write Address Master Driver Class10:58Watch
- 5.2AXI Write Address Slave Driver, Monitor & CoverageCourse : UVM in Systemverilog 2 : L5.2 : Writing AXI Write Address Slave Driver, Monitor & Coverage10:35Watch
- 5.3AXI Write Address AgentCourse : UVM in Systemverilog 2 : L5.3 : Writing AXI Write Address Agent Class10:57Watch
- 5.4AXI Write Data & Response AgentsCourse : UVM in Systemverilog 2 : L5.4 : Writing AXI Write Date & Write Response Agent Classes9:37Watch
- 5.5AXI Read Address & Data AgentsCourse : UVM in Systemverilog 2 : L5.5 : Writing AXI Read Address and Read Data Agent Classes6:04Watch
- 5.6AXI Protocol Checker & Coverage ComponentCourse : UVM in Systemverilog 2 : L5.6 : Writing AXI Protocol Checker and Coverage Classes in UVM11:04Watch
- 5.7Writing Complete AXI AgentCourse : UVM in Systemverilog 2 : L5.7 : Writing Complete AXI Agent Class in UVM15:34Watch
06Summary1/1 lessons · 2m
- 6.1SummaryCourse : UVM in Systemverilog 2 : L6.1 : Summary2:25Watch